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| EM78P870 8-BIT MICRO-CONTROLLER Version 1.5 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5630118 Version History Specification Revision History Version EM78P870 1.0 1.1 Content Initial version 1.Update feature description 2.Update Fig.2, Fig.3 3.Add test pin 4.Update operational register table list 5.Update R6 page1, R7 page1, R8 page1, R9 page1, RD page1, IOC6 page1 6.Update initial condition 7.Update application circuit 8.Update RE page1, IOCE page 2 4K Data RAM , No Data ROM Add DED function Remove DED function Remove comparator's 2.0V build-in reference voltage Remove Idle mode Release Date 2001/07/12 2001/08/29 1.2 1.3 1.4 1.5 2001/9/28 2001/10/20 2003/7/1 2004/8/19 User Application Note 1. ROM, OTP, ICE ROM EM78870 OTP EM78P870 ICE EM78808 ICE 2. Main Function Difference RAM EM78870 2.5K x 8 EM78P870 4K x 8 3. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required. 4. RE page1 Bit6~Bit7 are Un-defined registers. These two bits are un-define and their values will variation. During calculation, please do not include these two bits. 5. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into idle or sleep mode, please switch MCU to green mode. 6. Please always keep RA page0 bit7 = 0 or un-expect error will happen!! EM78P870 8-bit OTP Micro-controller I.General Description The EM78P870 is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. There are 32Kx13 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. Integrated onto a single chip are on_chip watchdog (WDT), RAM, programmable real time clock /counter, internal interrupt, power down mode, LCD driver, build-in KEY TONE clock generation, Programming Tone generators, Serial Peripheral Interface(SPI), comparator and tri-state I/O. The EM78P870 provides a single chip solution to design a message_display. II.Feature CPU E E E E E E E E E E E E Operating voltage range : 2.5Va 5.5V 2.2V~5.5V(Normal mode), 2.0V~5.5V(Green mode) 32KN 13 on chip Program Electrical One Time Programmable Read Only Memory (OTP-ROM) 4KN 8 on chip data RAM 144 byte working register Up to 51 bi-directional tri-state I/O ports (32 shared with LCD Segment pins) IO with internal Pull high, wake-up and interrupt functions STACK: 32 level stack for subroutine nesting TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler COUNTER1: 8-bit counter with 8-bit prescaler can be an interrupt source COUNTER2: 8-bit counter with 8-bit prescaler can be an interrupt source Watch Dog : Programmable free running on chip watchdog timer CPU modes: Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on 12 interrupt source : 8 external , 4 internal Key Scan : Port key scan function up to 16x4 keys Sub-Clock: 32.768kHz crystal Main-clock: 3.5826MHz multiplied by 0.25, 0.5, 1 or 3 generated by internal PLL Key tone output (shared with IO) : 4kHz, 2kHz, 1kHz Comparator: 3-channel comparators, internal (16 level) or external reference voltage (shared with IO) Serial Peripheral Interface (SPI) : Interrupt flag available for the read buffer full, Programmable baud rates of communication, Three-wire synchronous communication. (shared with IO) 128-pin QFP or chip : EM78P870AH (POVD disable) , EM78P870BH (POVD enable), EM78P870H Operation Voltage 2.2Va 5.5V Programmable Tone1 and Tone2 generators Independent single tone generation for Tone1 and Tone2 Mixed dual tone generation by Tone1 and Tone2 with 2dB difference Maximum common driver pins : 16/24 Maximum segment driver pins : 80(SEG0..SEG79)/72(SEG8..SEG79) Shared COM16 ~ COM23 pins with SEG0 ~ SEG7 pins 1/4 bias for 8, 9 and 16 common mode and 1/5 bias for 24 common mode 1/8, 1/9, 1/16, 1/24 duty 16 Level LCD contrast control (software) Internal resistor circuit for LCD bias Internal voltage follower for better display 128-pin QFP : EM78P870AQ (POVD disable), EM78P870BQ (POVD enable), EM78P870H 130-pin die E E E E E E E E E E E E E E E E E E E E E E Programmable Tone Generators LCD (8x80, 9x80, 16x80, 24x72) Package type _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 1 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller III.Application Cordless phones or any telephone product with large LCD needed IV.Pin Configuration COM 16/SEG0 COM 15 COM 17/SEG1 COM 18/SEG2 COM 19/SEG3 COM 20/SEG4 COM 22/SEG6 COM 21/SEG5 COM 23/SEG7 COM 12 COM 11 127 126 COM 13 COM 14 COM 10 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 18 19 20 21 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 41 42 63 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG17 SEG16 SEG8 SEG9 105 106 108 109 110 107 125 124 123 122 121 120 119 118 116 117 115 114 123 112 111 COM 9 COM 8 COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 VC5 VC4 VC3 VC2 VC1 XIN XOUT VDD AVDD PLLC TONE AVSS GND TEST /RESET P70/INT0 P71/INT0 P72/INT0 P73/INT0 P74/INT1 P75/INT1 P76/INT1 P77/INT2 P60/SCK P61/SDO P62/SDI P63/CM P1 P64/CM P2 P65/CM P3 P66 P67/KTONE 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 88 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/PB0 SEG49/PB1 SEG50/PB2 SEG51/PB3 SEG52/PB4 SEG53/PB5 SEG54/PB6 SEG55/PB7 SEG56/PC0 SEG57/PC1 SEG58/PC2 P57 SEG79/P97 SEG78/P96 SEG77/P95 SEG76/P94 SEG75/P93 SEG74/P92 SEG73/P91 SEG72/P90 P56 SEG71/P87 SEG70/P86 SEG69/P85 SEG68/P84 SEG67/P83 SEG66/P82 SEG65/P81 SEG64/P80 SEG63/PC7 P55 SEG62/PC6 SEG61/PC5 SEG60/PC4 Fig.1 Pin assignment (128-pin QFP ) _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 2 SEG59/PC3 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller COM 17/SEG1 COM 16/SEG0 COM 18/SEG2 COM 19/SEG3 COM 20/SEG4 COM 21/SEG5 COM 22/SEG6 COM 23/SEG7 COM 12 COM 11 129 128 COM 13 COM 14 COM 15 COM 10 130 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 18 19 20 21 22 23 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG10 SEG11 SEG12 SEG13 SEG14 SEG17 SEG16 SEG15 SEG9 SEG8 108 109 107 127 126 125 123 124 122 121 120 119 118 117 115 116 114 113 112 110 111 106 COM 9 COM 8 COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 VC5 VC4 VC3 VC2 VC1 XIN XOUT VDD AVDD PLLC TONE NC NC AVSS GND TEST /RESET P70/INT0 P71/INT0 P72/INT0 P73/INT0 P74/INT1 P75/INT1 P76/INT1 P77/INT2 P60/SCK P61/SDO P62/SDI P63/CM P1 P64/CM P2 P65/CM P3 P66 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/PB0 SEG49/PB1 SEG50/PB2 SEG51/PB3 SEG52/PB4 SEG53/PB5 SEG54/PB6 SEG55/PB7 SEG56/PC0 SEG57/PC1 SEG58/PC2 SEG59/PC3 P57 SEG79/P97 SEG78/P96 SEG77/P95 SEG76/P94 SEG75/P93 SEG74/P92 SEG73/P91 SEG72/P90 SEG71/P87 SEG70/P86 SEG69/P85 SEG68/P84 SEG67/P83 SEG66/P82 SEG65/P81 SEG64/P80 SEG63/PC7 SEG62/PC6 SEG61/PC5 P67/KTONE Fig.1.2 Pin assignment (130-pin die ) _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 3 SEG60/PC4 P55 P56 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller OTP writer PIN NAME 1.VDD 2.VPP 3.DINCK 4.ACLK 5.PGM 6.OE 7.DATA 8.GND MASK ROM PIN NAME VDD,AVDD /RESET P77 P76 P75 P74 P73 VSS,AVSS,TEST P.S. V.Functional Block Diagram CPU DATA RAM CONTROL REGISTER TIMING CONTROL TIMER TCC COUNTER 1 COUNTER 2 WDT LCD DRIVER LCD IO PORT KEY TONE COMPARATOR SERIAL I/O PROG. TONE GEN. I/O PROGRAM ROM Fig.2 Block diagram1 Xin Xout PLLC W DT timer Oscillator timing control R1(TCC) GENERAL RAM R4 Interruption control prescalar Instruction register R3 R5 ALU ROM R2 STACK Control sleep and wake-up on I/O port ACC Instruction decoder DATA & CONTROL BUS DATA RAM PORT5 IOC5 R5 PORT6 IOC6 R6 PORT7 IOC7 R7 PORT8 IOC8 R8 PORT9 IOC9 R9 PORTB IOCB RB PORTC IOCC RC KEY TONE PROG. TONE GEN. COMPARATOR SERIAL I/O P55~P57 P60~P67 P70~P77 P80~P87 P90~P97 PB0~PB7 PC0~PC7 Fig.3 Block diagram2 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 4 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller VI.Pin Descriptions PIN POWER VDD AVDD GND AVSS CLOCK XIN XOUT PLLC LCD COM0..COM15 COM16..COM23 SEG0..SEG7 SEG8...SEG47 SEG48..SEG55 SEG56..SEG63 SEG64..SEG71 SEG72..SEG79 VC1..VC5 TONE, KTONE TONE KTONE SERIAL IO SCK SDO SDI COMPARATOR CMP1 CMP2 CMP3 IO P55 ~P57 P60 ~P67 P70 ~ P77 I/O POWER POWER DESCRIPTION Digital power Analog power Digital ground Analog ground Input pin for 32.768kHz oscillator Output pin for 32.768kHz oscillator Phase loop lock. Connect a capacitor 0.01u to 0.047u with GND. Common driver pins of LCD drivers COM16 to COM23 are shared with SEG0 to SEG7 Segment driver pins of LCD drivers SEG0 to SEG7 are shared with COM16 to COM23 SEG48 to SEG79 are shared with IO PORT I O I O O (SEG0..SEG7) O (COM16..COM23) O O (I/O : PORTB) O (I/O : PORTC) O (I/O : PORT8) O (I/O : PORT9) I O O (PORT67) IO (PORT60) O (PORT61) I (PORT62) I (PORT63) I (PORT64) I (PORT65) I/O I/O I/O Reference voltage input. Each one connect a capacitor (0.1u) with GND. Programming tone output pin Key tone output. Shared with PORT67 Master : output pin, Slave : input pin. This pin is shared with PORT60. Output pin for serial data transferring. This pin is shared with PORT61. Input pin for receiving data. This pin shared with PORT62. Comparator input pins. Shared with PORT63, PORT64 and PORT65. P80 ~ P87 P90 ~ P97 PB0 ~ PB7 PC0 ~ PC7 INT0 I/O I/O I/O I/O PORT70..73 INT1 PORT74..76 PORT 5 can be INPUT or OUTPUT port each bit. PORT 6 can be INPUT or OUTPUT port each bit. Internal pull high. PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Auto key scan function. Interrupt function. PORT 8 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT 9 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT B can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT C can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. Interrupt source which has the same interrupt flag. Any pin from PORT70 to PORT73 has a falling edge signal, it will generate a interruption. Interrupt source which has the same interrupt flag. Any pin from PORT74 to PORT76 has a falling edge signal, it will generate a interruption. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 5 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller INT2 TEST /RESET PORT77 I I Interrupt source. Once PORT77 has an edge triggering signal (controlled by CONT register), it will generate a interruption. Test pin into test mode for factory test only. Connect it ground in application. Low reset _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 6 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller VII.Functional Descriptions VII.1 Operational Registers ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F R0 R1(TCC buffer) R2(PC) R3(7) R3(STATUS ) R4(RSR, BANK SELECT) R5(PORT57.. PORT55, Program ROM PAGE) R6(PORT6) R7(PORT7) R8(PORT8) R9(PORT9) RA(CPU MODE,CLOCK, WDT control) RB(PORTB) RC(PORTC) RD(Comparator control) RE(Key scan , LCD control) RF(Interrupt flag) R4(SPI status and control) R5(SPI data buffer) R6 (Unused) R7(Unused) R8(Unused) R9(LCDA8) RA(LCD RAM address) RB (LCD RAM data buffer) RC(DATA RAM data buffer) RD(DATA RAM address address7..address0) RE(DATA RAM address address12..address8) IOC5(IOC55,56,57, P8S,P9S,PBS PCS) IOC6(PORT6 IO control) IOC7 (PORT7 IO control) IOC8 (PORT8 IO control) IOC9 (PORT9 IO control) IOCA(COUNTER1,2 prescaler and source) IOCB(PORTB IO control) IOCC(PORTC IO control) IOCD(COUNTER1 PRESET) IOCE(COUNTER2 PRESET) IOCF(Interrupt control) CONTROL REGISTER (PAGE2) R3(5,6) LCD RAM BANK0 , BANK1, BANK2 , BANK3 32X8 32X8 32x8 32x8 COMMOM REGISTERS RA PAGE1 => address RB PAGE1 =>data DATA RAM RD PAGE1 => address7..0 RE PAGE1 => address12..8 RC PAGE1 =>data IOC6(Port s/w, LCDDV, CDAL) IOCA(PORT7 pull high) IOCB(PORT6 pull high) IOCC(Tone1) IOCD(Tone2) IOCE(Comparator ref., PORT switch) IOC5(Key tone, LCD bias bias) IOC6(Port s/w, LCDDV, CDAL) IOC7(key strobe , seg15 .. seg8) IOC8(key strobe, seg23.. seg16) R3(5,6) REGISTER (PAGE0) REGISTER (PAGE1) CONTROL REGISTER (PAGE0) CONTROL REGISTER (PAGE1) 16-byte GENERAL REGISTERS R4(7,6) Fig.4 control register configuration VII.2 Operational Register Table List (1) Paged registers (R PAGE0, RPAGE1, IOC PAGE0, IOC PAGE1) R0~R4 and RF are unpaged registers. R PAGE0 Addr 00 01 02 03 Name R0 R1 R2 R3 C DC Z T P IOCPAGE IOC6P1S Bit Function Indirect addressing register TCC Program counter Status, Page selection Carry flag Auxiliary carry flag Zero flag Time-out bit Power down bit Change IOC5 ~ IOCE to PAGE0/PAGE1 Change IOC6 PAGE1 to option-A/option-B 0 1 2 3 4 5 6 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 7 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller PAGE R4 RSR0~RSR5 RB0~ RB1 R5 PAGE0 PS0~PS4 P55~P57 R6 PAGE0 P60~P67 R7 PAGE0 P70~P77 R8 PAGE0 P80~P87 R9 PAGE0 P90~P97 RA PAGE0 WDTEN 1 0 CLK0~CLK1 PLLEN 0 RB PAGE0 PB0~PB7 RC PAGE0 PC0~PC7 RD PAGE0 CMP_B0~CMP_B3 CMPS0~CMPS1 CMPFLAG CMPEN RE PAGE0 LCDM0~LCDM1 LCD0~LCD1 KEYSCAN KEYSTRB KEYCHK 1 RF TCIF CNT1 CNT2 INT0 INT1 INT2 0 RBF 7 0~5 6~7 0~4 5~7 0~7 0~7 0~7 0~7 0 1~2 3 4~5 6 7 0~7 0~7 0~3 4~5 6 7 0~1 2~3 4 5 6 7 0 1 2 3 4 5 6 7 Change R4 ~ RE to PAGE0/PAGE1 RAM selection for common registers Indirect addressing for common registers R20 ~ R3F Bank selection bits for common registers R20 ~ R3F PORT5 I/O data register, Program page selection Program page selection bits 3-bit PORT5(5~7) I/O data register PORT6 I/O data register 8-bit PORT6(0~7) I/O dada register PORT7 I/O data register 8-bit PORT7(0~7) I/O dada register PORT8 I/O data register 8-bit PORT8(0~7) I/O dada register PORT9 I/O data register 8-bit PORT9(0~7) I/O dada register CPU power saving, PLL, Main clock selection, Watchdog timer Watchdog control bit Unused Unused Main clock selection bits PLL's power control bit which is CPU mode control register Please clear this bit to 0 PORTB I/O dada register 8-bit PORTB(0~7) I/O dada register PORTC I/O dada register 8-bit PORTC(0~7) I/O dada register Comparator control Reference voltage selection of internal bias circuit for comparator Channel selection from CMP1 to CMP3 for comparator Comparator output flag Enable control bit of comparator Key scan, LCD control LCD common mode, bias select and COM/SEG switch control LCD operation function definition Key scan function enable control bit Key strobe enable control bit Key check enable control bit Unused Interrupt status register Timer overflow interrupt flag for TCC Timer overflow interrupt flag for COUNTER1 Timer overflow interrupt flag for COUNTER2 Interrupt flag for external INT0 pin Interrupt flag for external INT1 pin Interrupt flag for external INT2 pin Unused Interrupt flag for SPI data complete 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 8 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller R PAGE1 Addr Name 04 R4 PAGE1 SBR0~SBR2 SCES SE SRO SPIE RBF 05 R5 PAGE1 SPIB0~SPIB7 06 07 08 09 R9 PAGE1 0 LCDA8 RA PAGE1 LCDA0~LCDA7 RB PAGE1 LCDD0~LCDD7 RC PAGE1 RAMD0~RAMD7 RD PAGE1 RAMA0~RAMA7 RE PAGE1 RAMA8~RAMA12 0 X X Bit 0~2 3 4 5 6 7 0~7 Function SPI control register SPI baud rate selection bits SPI clock edge selection bit SPI shift enable bit SPI read overflow bit SPI enable bit SPI read buffer full flag SPI data buffer SPI data buffer LCD address MSB bit, Data ROM address Unused MSB of LCD address for LCD RAM reading or writing LCD address LCD address for LCD RAM reading or writing LCD data buffer LCD data buffer for LCD RAM reading or writing Data RAM data buffer for RAM reading or writing Data RAM address0 ~ address7 Data RAM address0 ~ address7 for RAM reading or writing Data RAM address8 ~ address12 Data RAM address8 ~ address12 for RAM reading or writing Unused Undefined. It's value is variable. Undefined. It's value is variable. 0~6 7 0~7 0~7 0~7 0~7 0~4 5 6 7 0A 0B 0C 0D 0E IOC PAGE0 Addr Name 05 IOC5 PAGE0 P8SL P8SH P9SL P9SH 0 IOC55~IOC57 06 IOC6 PAGE0 IOC60~IOC67 07 IOC7 PAGE0 IOC70~IOC77 08 IOC8 PAGE0 IOC80~IOC87 Bit 0 1 2 3 4 5~7 0~7 0~7 0~7 Function PORT5 I/O control register, PORT switch Switch low nibble I/O PORT8 or LCD segment output Switch high nibble I/O PORT8 or LCD segment output Switch low nibble I/O PORT9 or LCD segment output Switch high nibble I/O PORT9 or LCD segment output Unused PORT5(5~7) I/O direction control register PORT6 I/O control register PORT6(0~7) I/O direction control register PORT7 I/O control register PORT7(0~7) I/O direction control register PORT8 I/O control register PORT8(0~7) I/O direction control register _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 9 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller 09 0A IOC9 PAGE0 IOC90~IOC97 IOCA PAGE0 C1P0~C2P2 CNT1S C2P0~C2P2 CNT2S IOCB PAGE0 IOCB0~IOCB7 IOCC PAGE0 IOCC0~IOCC7 IOCD PAGE0 CN10~CN17 IOCE PAGE0 CN20~CN27 IOCF TCIF CNT1 CNT2 INT0 INT1 INT2 0 RBF PORT9 I/O control register PORT9(0~7) I/O direction control register Counter1 and Counter2 clock and scale setting Counter1 scaling Counter1 clock source Counter2 scaling Counter2 clock source PORTB I/O control register PORTB(0~7) I/O direction control register PORTC I/O control register PORTC(0~7) I/O direction control register Counter1 data buffer Counter1 data buffer that user can read and write Counter2 data buffer Counter2 data buffer that user can read and write Interrupt mask register Interrupt enable bit for TCC Interrupt enable bit for COUNTER1 Interrupt enable bit for COUNTER2 Interrupt enable bit for external INT0 pin Interrupt enable bit for external INT1 pin Interrupt enable bit for external INT2 pin Unused Interrupt enable bit for SPI data complete 0~7 0~2 3 4~6 7 0~7 0~7 0~7 0~7 0 1 2 3 4 5 6 7 0B 0C 0D 0E 0F IOC PAGE1 Addr Name 05 IOC5 PAGE1 BIAS0~BIAS3 0 KTS KT0~KT1 06 IOC6 PAGE1 07 IOC7 PAGE1 STRB8~STRB15 08 IOC8 PAGE1 STRB16~STRB23 09 0A IOCA PAGE1 PH70~PH77 0B IOCB PAGE1 PH60~PH67 0C IOCC PAGE1 T10~T17 0D IOCD PAGE1 T20~T27 0E IOCE PAGE1 Bit 0~3 4 5 6~7 Function Key tone control, LCD bias control LCD operation voltage selection Unused Key tone output switch Key tone output frequency and its power control Key strobe control register Key strobe control bits Key strobe control register Key strobe control bits PORT7 pull high control register PORT7(0~7) pull high control register PORT6 pull high control register PORT6(0~7) pull high control register TONE1 control register Tone generator1's frequency divider and power control TONE2 control register Tone generator2's frequency divider and power control Comparator reference voltage type, PORT switch 0~7 0~7 0~7 0~7 0~7 0~7 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 10 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller 0 CMPIN1 CMPIN1 CMPIN1 CMPREF 0~3 4 5 6 7 Unused Switch for controlling PORT63 IO PORT or a comparator input Switch for controlling PORT64 IO PORT or a comparator input Switch for controlling PORT65 IO PORT or a comparator input Switch for comparator reference voltage type (2) Unpage registers (Common registers) In addition to R0~R4 and RF, other unpaged registers are as list below. Addr 10 : 1F 20 : 3F Name R10 : R1F R20 : R3F Bit Function Common register : Common register 4 - bank common register : 4 - bank common register IOC PAGE 2 06 IOC6 PAGE2 0 LCDDV0~LCDDV1 PBS PCSL PCSH IOCE PAGE2 DEDTHD DEDPWR DEDCLK WUEDD EDGE DED VRSEL 0~2 3~4 5 6 7 0 1 2 4 5 6 7 PORT switch, LCD driving ability control Unused LCD driver's driving ability control Switch I/O PORTB or LCD segment output Switch low nibble I/O PORTC or LCD segment output Switch high nibble I/O PORTC or LCD segment output Minimum detection threshold of SED Power control of DED operating clock of DED Wake-up control of DED output data edge control of DED output data interrupt mask for DED Reference voltage VR selection bit for Comparator 0E (3) Unaddressable register Name ACC CONT PSR0~PSR2 PAB TS INT INT_EDGE Bit Function Accumlator : Internal data transfer and instruction operand holding Control register TCC/WDT prescaler bits Prescaler assignment bit (unused) TCC signal source INT enable flag Interrupt edge type of P70 0~2 3 4 5 6 7 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 11 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller VII.3 Operational Register Detail Description R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov a,@0x20 ;store a address at R4 for indirect addressing Mov 0x04,A Mov a,@0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00,A R1 (TCC) TCC data buffer. Increased by 16.384kHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register. R2 (Program Counter) The structure is depicted in Fig. 5. Generates 32K x 13 on-chip PROGRAM ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A14) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction. If a interrupt trigger, PROGRAM ROM will jump to address8 at page0. The CPU will store ACC,R3 status and R5 PAGE automatically, it will restore after instruction RETI. R5(PAGE) CALL and INTERRUPT A9 A8 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 : : STACK30 STACK31 STACK32 PC A14 A13 A12 A11 A10 00000 PAGE0 0000~03FF 00001 PAGE1 0400~07FF 00010 PAGE2 0800~0BFF store ACC,R3,R5(PAGE) restore 11110 11111 PAGE30 7800~7BFF PAGE31 7C00~7FFF Fig.5 Program counter organization _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 12 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller R3 (Status Register) 7 6 5 4 3 2 1 0 PAGE IOCP1S IOCPAGE T P Z DC C Bit 0 (C) : Carry flag Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag Bit 3 (P) : Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 page0 / page1 Bit 6(IOCP1S) : change IOC PAGE1 and PAGE2 to another option register Please refer to Fig.4 control register configuration for details. 0/1 page1 /page2 Bit 6(IOCP1S) X 0 1 Bit 5 (IOCPAGE) 0 1 1 IOC PAGE SELECT PAGE 0 PAGE 1 PAGE 2 Bit 7(PAGE) : change R4 ~ RE to another page Please refer to Fig.4 control register configuration for details. 0/1 page0 / page1 R4 (RAM selection for common registers R20 ~ R3F, SPI control) PAGE0 (RAM selection register) 7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F).. Please refer to Fig.4 control register configuration for details. PAGE1 (SPI control register) 7 6 5 4 3 2 1 0 RBF SPIE SRO SE SCES SBR2 SBR1 SBR0 Fig. 6 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 13 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller basis of both the clock rate and the selected edge. SDO SDI Master Device R5 page1 SPIR register SPIW register Salve Device SPIS Reg Bit7 Bit 0 SDI SDO SPI module SCK SCK Fig.6 Single SPI Master / Salve Communication Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits SBRS2(Bit 2) 0 0 0 0 1 1 1 1 SBRS1(Bit 1) 0 0 1 1 0 0 1 1 SBRS0(Bit 0) 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Master Slave x x Baud rate Fsco Fsco/2 Fsco/4 Fsco/8 Fsco/16 Fsco/32 Bit 4 (SE) : SPI shift enable bit 1 0 Start to shift, and keep on 1 while the current byte is still being transmitted. Reset as soon as the shifting is complete, and the next byte is ready to shift. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 14 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller 1 A new data is received while the previous data is still being hold in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB register even if the transmission is implemented only. No overflow 0 Bit 7 (RBF) : SPI read buffer full flag 1 0 Receive is finished, SPIB is full. Receive is not finish yet, SPIB is empty. Read R5 RBF RBFI Write R5 SPIWC SPIR reg. SPIW reg. set to 1 SPIE Buffer Full Detector SDI SDI/P62 MUX SPIS reg. PORT62 bit 0 SDO shift right bit 7 SDO/P61 SPIC reg. (R4 page1) MUX PORT61 Edge Select SPIE 0 3 SBR0 ~SBR2 SBR2~SBR0 3 2 Noise Filter Clock Select Tsco 16.38kHz Prescaler 4, 8, 16, 32, 64, 128 Edge Select SCK SCK PORT60 MUX SCK/P60 SPIE Fig.7 SPI structure SPIC reg. : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock. RBF : Set by buffer full detector, and reset in software. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 15 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller RBFI : Interrupt flag. Set by buffer full detector, and reset in software. Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete. SE : Loads the data in SPIW register, and begin to shift SPIE : SPI control register SPIS reg. : Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the RBFI(Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is complete. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1 if the communication is still under going. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programming the clock frequency/rates and sources. Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting clock. Edge Select : Selecting the appropriate clock edges by programming the SCES bit SCK (SCES=0) SCK (SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDO SDI RBF Shift data in Shift data out Clear by software Fig.8 SPI timing _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 16 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller R5 (PORT5 I/O data, Program page selection, SPI data) PAGE0 (PORT5 I/O data register, Program page register) 7 6 5 4 3 2 1 0 R57 R56 R55 PS4 PS3 PS2 PS1 PS0 Bit 0 ~ Bit 4 (PS0 ~ PS4) : Program page selection bits PS4 PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 0 Page 0 0 0 0 0 1 Page 1 0 0 0 1 0 Page 2 0 0 0 1 1 Page 3 : : : : : : : : : : : : 1 1 1 1 0 Page 30 1 1 1 1 1 Page 31 User can use PAGE instruction to change page to maintain program page by user. Bit 5 ~ Bit 7 (P55 ~ P57) : 3-bit PORT5(5~7) I/O data register User can use IOC register to define input or output each bit. PAGE1 (SPI data buffer) 7 6 5 4 3 2 1 0 SPIB7 SPIB6 SPIB5 SPIB4 SPIB3 SPIB2 SPIB1 SPIB0 Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data from SPIR register. Please refer to figure7 R6 (PORT6 I/O data) PAGE0 (PORT6 I/O data register) 7 6 5 4 3 2 P67 P66 P65 P64 P63 P62 Bit 0 ~ Bit 8 (P60 ~ P67) : 8-bit PORT6(0~7) I/O data register User can use IOC register to define input or output each bit. 1 P61 0 P60 R7 (PORT7 I/O data) PAGE0 (PORT7 I/O data register) 7 6 5 4 3 2 P77 P76 P75 P74 P73 P72 Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register User can use IOC register to define input or output each bit. 1 P71 0 P70 R8 (PORT8 I/O data) PAGE0 (PORT8 I/O data register) 7 6 5 4 3 2 P87 P86 P85 P84 P83 P82 Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register User can use IOC register to define input or output each bit. 1 P81 0 P80 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 17 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller R9 (PORT9 I/O data, extra LCD address bit) PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register User can use IOC register to define input or output each bit. PAGE1 (LCD address MSB bit) 7 6 5 4 3 2 1 0 LCDA8 0 0 0 0 0 0 0 Bit 0 ~ Bit 6 = 0 : unused Bit 7 (LCDA8) : MSB of LCD address for LCD RAM reading or writing Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0. For LCD address access over 0xFFH, set this bit to "1"; otherwise set this bit to "0". RA (CPU power saving, PLL, Main clock selection, Watchdog timer, LCD address) PAGE0 (CPU power saving bit, PLL, Main clock selection bits, Watchdog timer enable bit) 7 6 5 4 3 2 1 0 PLLEN CLK1 CLK0 0 1 1 WDTEN 0 Bit 0 (WDTEN) : Watch dog control register User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler. 0/1 disable/enable Bit 1~ Bit 2 = 1 : unused Bit 3 = 0 : unused Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. PLLEN 1 1 1 1 0 0 0 0 CLK1 0 0 1 1 Don't care Don't care Don't care Don't care CLK0 0 1 0 1 don't care don't care don't care don't care Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock CPU clock 895.658kHz 895.658kHz (Normal mode) 1.7913MHz 1.7913MHz (Normal mode) 10.7479MHz 10.7479MHz (Normal mode) 3.5826MHz 3.5826MHz (Normal mode) don't care 32.768kHz (Green mode) don't care 32.768kHz (Green mode) don't care 32.768kHz (Green mode) don't care 32.768kHz (Green mode) Bit 6 (PLLEN) : PLL enable control bit It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency,main clock); otherwise, it will run at green mode (low frequency, 32768 Hz). 0/1 disable/enable _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 18 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller 3.5826M Hz to analog circuit PLL / / x x 4 =>895.658kHz 2 =>1.7913M Hz 1 =>3.5826M Hz 3 =>10.7479M Hz 1 switch System clock 0 Sub-clock 32.768kHz ENPLL CLK1 ~ CLK0 Fig.9. The relation between 32.768kHz and PLL Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!The status after wake-up and the wake-up sources list as the table below. Wakeup signal SLEEP mode RA(7,6)=(0,0) + SLEP No function GREEN mode RA(7,6)=(x,0) no SLEP Interrupt (jump to address 8 at page0) NORMAL mode RA(7,6)=(x,1) no SLEP Interrupt (jump to address 8 at page0) TCC time out IOCF bit0=1 And "ENI" COUNTER1 time out IOCF bit1=1 And "ENI" COUNTER2 time out IOCF bit2=1 And "ENI" WDT time out PORT7 IOCF bit3 or bit4 or bit5 =2 And "ENI" No function Interrupt Interrupt (jump to address 8 (jump to address 8 at page0) at page0) Interrupt Interrupt (jump to address 8 (jump to address 8 at page0) at page0) RESET and Jump to address 0 Interrupt (jump to address 8 at page0) RESET and Jump to address 0 Interrupt (jump to address 8 at page0) No function RESET and Jump to address 0 RESET and Jump to address 0 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 19 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller PAGE1 (LCD address) 7 6 5 4 3 2 1 0 LCDA7 LCDA6 LCDA5 LCDA 4 LCDA 3 LCDA 2 LCDA 1 LCDA 0 Bit 0 ~ Bit 7 (LCDA0 ~ LCDA7) : LCD address for LCD RAM reading or writing The data in the LCD RAM correspond to the COMMON and SEGMENT signals as the table . COM23 ~ COM16 COM15 ~COM8 COM7 ~ COM0 (set R9 PAGE1 bit7=1) (set R9 PAGE1 bit7=0) (set R9 PAGE1 bit7=0) Address 100H Address 80H Address 00H SEG0 Address 101H Address 81H Address 01H SEG1 Address 102H Address 82H Address 02H SEG1 : : : : : : : : : : : : Address 14EH Address CEH Address 4EH SEG78 Address 14FH Address CFH Address 4FH SEG79 Address 150H Address D0H Address 50H Empty : : : : Address 17FH Address FFH Address 7FH Empty RB (PORTB I/O data, LCD data) PAGE0 (PORTB I/O data register) 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit PORTB(0~7) I/O data register User can use IOC register to define input or output each bit. PAGE1 (LCD data buffer) 7 6 5 4 3 2 1 0 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 Bit 0 ~ Bit 7 (LCDD0 ~ LCDD7) : LCD data buffer for LCD RAM reading or writing Ex. MOV A,@0 MOV R9_PAGE1,A MOV RA_PAGE1,A ;ADDRESS MOV A,@0XAA MOV RB_PAGE1,A ;WRITE DATA 0XAA TO LCD RAM MOV A,RB_PAGE1 ;READ DATA FROM LCD RAM : RC (PORTC I/O data, Data RAM data) PAGE0 (PORTC I/O data register) 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit PORTC(0~7) I/O data register User can use IOC register to define input or output each bit. PAGE1 (Data RAM data buffer) 7 6 5 4 3 2 1 0 RAMD7 DRAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 Bit 0 ~ Bit 7 (RAMD0 ~ RAMD7) : Data RAM data buffer for RAM reading or writing. Ex. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 20 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller MOV MOV MOV MOV MOV MOV MOV : A,@1 RD_PAGE1,A A,@0 RE_PAGE1,A A,@0x55 RC_PAGE1,A A,RC_PAGE1 ;write data 0x55 to DATA RAM which address is "0001". ;read data RD (Comparator control, Data RAM address(0 ~ 7)) PAGE0 (Comparator control bits) 7 6 5 4 3 2 1 0 CMPEN CMPFLAG CMPS1 CMPS0 CMP_B3 CMP_B2 CMP_B1 CMP_B0 If user define PORT63 , PORT64 or PORT65 (by CMPIN1, CMPIN2, CMPIN3 at IOCE page1) as a comparator input or PORT6. User can use this register to control comparator's function. Bit 0 ~ Bit 3 (CMP_B0 ~ CMP_B3) : Reference voltage selection of internal bias circuit for comparator. Reference voltage for comparator = VDD x ( n + 0.5 )/ 16 , n = 0 to 15 Bit 4 ~ Bit 5 (CMPS0 ~ CMPS1) : Channel selection from CMP1 to CMP3 for comparator CMPS1 0 0 1 1 CMPS0 0 1 0 1 Input CMP1 CMP2 CMP3 Reserved _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 21 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Bit 6 (CMPFALG) : Comparator output flag 0 Input voltage < reference voltage 1 Input voltage > reference voltage Bit 7 (CMPEN) : Enable control bit of comparator. 0/1 disable/enable The relation between these registers shown in Fig.10. CMP1 MUX PORT63 P63/CMP1 CMPIN1 P64/CMP2 CMP2 MUX PORT64 CMPIN2 P65/CMP3 CMP3 MUX PORT65 2 CMPS1 CMPS0 1 0 MUX MUX + CMPFLAG CMPIN3 VR VDD CMPREF CMPEN 1/2R 1111 R 1110 R 0000 1/2R 4 CMP_B3 to CMP_B0 MUX Fig.10. Comparator circuit _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 22 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller CMPEN CMP1 to CMP3 reference voltage Setup time 10us CPU clock CMPFLAG Compare start Compare end Fig.11. Comparator timing PAGE1 (Data RAM address0 ~ address7) 7 6 5 4 3 2 1 0 RAMA7 RAMA6 RAMA5 RAMA4 RAMA3 RAMA2 RAMA1 RAMA0 Bit 0 ~ Bit 7 (RAMA0 ~ RAMA7) : Data RAM address (address0 to address7) for RAM reading or writing RE (Key scan, LCD control, Data RAM address(8 ~ 11)) PAGE0 (Key scan control, LCD control) 7 6 5 4 3 2 1 0 KEYCHK KEYSTRB KEYSCAN LCD1 LCD0 LCDM1 LCDM0 1 Bit 0 ~ Bit 1 (LCDM0 ~ LCDM1) : LCD common mode, bias select and COM/SEG switch control bits LCDM1, LCDM0 0,0 0,1 1,0 1,1 COM output mode LCD bias 16 common 9 common 8 common 24 common 1/4 bias 1/4 bias 1/4 bias 1/5 bias COM/SEG switch SEG0 ~ SEG7 select SEG0 ~ SEG7 select SEG0 ~ SEG7 select COM16 ~ COM23 select _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 23 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller The controller can drive LCD directly. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins and LCD operating bias pins. Duty, the number of segment , the number of common and frame frequency are determined by LCD mode register RE PAGE0 Bit 0~ Bit 1. When 8, 9 or 16 LCD commons are used, LCD operating bias pins VC1, VC2, VC4 and VC5 need to be connected 0.1uF capacitors to the ground (VC3 is not necessary). When 24 LCD common is used, all LCD operating bias pins VC1 ~ VC5 need to be connected 0.1uF capacitors to the ground. LCD driver can be controlled as different driving ability (refer to IOC6 PAGE1 Option-B register). The basic structure contains a timing control which uses the basic frequency 32.768kHz to generate the proper timing for different duty and display access. RE PAGE1 register is a command register for LCD driver and display. The LCD display (disable, enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving duty is decided by RE PAGE Bit 0 ~ Bit 2. LCD display data is stored in data RAM which address and data access controlled by registers R9, RA PAGE1 and RB PAGE1. User can regulate the contrast of LCD display by IOC5 PAGE1 (BIAS3..BIAS0). Up to 16 levels contrast is convenient for better display. And the internal voltage follower can afford large driving source. COM signal : The number of COM pins varies according to the duty cycle used, as following: in 1/8 duty mode COM8 ~ COM15 must be open. In 1/9 duty mode COM9~ COM15 must be open in 1/16 duty mode COM0 ~ COM15 pins must be used. in 1/24 duty mode COM0 ~ COM23 pins must be used. duty 1/8 1/9 1/16 1/24 COM0 ~ COM7 o o o o COM8 x o o o COM9 x x o o .. .. .. .. .. COM15 COM15 ~ COM23 x x x x o x o o x : open, o : select SEG signal: The segment signal pins are connected to the corresponding display RAM. The high byte to the low byte Bit 0 ~ Bit 7 are correlated to COM0 ~ COM23 respectively . When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select signal is sent to the corresponding segment pin. Bit 4 (KEYSCAN) : Key scan function enable control bit 0/1 disable/enable If you enable key scan function LCD waveform will has a small pulse within a period like Fig.12. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 24 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller COM2 V1 V2 V4 V5 GND SEG V1 V2 V4 V5 GND 30us V1 V2 V4 V5 GND Fig.12. keyscan waveform for 1/8, 1/9, 1/16 duty Bit 5 (KEYSTRB) : Key strobe enable control bit 0/1 disable/enable key strobe signal , if you set this bit , segment will switch to strobe signal temporally and output zero signal ( one instruction long ) one by one from segment 8 to segment 23. During one segment strobe time, CPU will check port7(0:3) equal to "1111" or not. If not, CPU will latch a zero at IOC7 PAGE1 and IOC8 PAGE1 one by one depends on which segment strobe. After strobe, this bit will be cleared . Fig.13 is key strobe signal. One instruction REGISTER STROBE SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 IOC7(0) IOC7(1) IOC7(2) IOC7(3) IOC7(4) IOC7(5) IOC7(6) IOC7(7) IOC8(0) IOC8(1) IOC8(2) IOC8(3) IOC8(4) IOC8(5) IOC8(6) IOC8(7) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Fig.13 key strobe signal _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 25 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Bit 6 (KEYCHK) : Key check enable control bit 0 disable key check function. 1 enable key check function. SEG8 to SEG23 will keep low level. Figure 14 is relationship between KEYSCAN, KEYSTROBE , KETCHECK and segments. And figure 16 is key scan flow by interrupt trigger. RELATION BETWEEN S(8:23) , KEYSCAN, KEY STROBE, KEY CHECK KEY SCAN PULSE KEY SCAN CONTROL 0 SEGMENT(8:23) KEY STROBE SIGNAL MUX 1 0 GND 1 MUX KEYSTROBE KEYCHECK Fig.14 KEYSCAN, KEYSTROBE , KETCHECK and segments. Bit 7 = 1 : unused _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 26 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Set port7(3:0) input (IOC7 (7:0) = " 0x0f " ) set IOC page1 (BS R3,IOC_PAGE) port7 pull high (IOCA=0x0f) set IOC page0 (BC R3,IOC_PAGE) enable key scan signal (RE bit4=1) set INT0 interrupt ENI N Interrupt occur? Y Enable main clock (Normal mode) program delay enable RE(6) key check Read port7 ( column key ) disable RE(6) key check set strobe function enable RE (5) keystrobe program delay read IOC7,IOC8 (row key) Execution key function Get the key location Fig.15 key scan flow by interrupt trigger PAGE1 (Data RAM address8 ~ address11) 7 6 5 4 3 2 1 0 X X 0 0 RAMA11 RAMA10 RAMA9 RAMA8 Bit 0 ~ Bit 3 (RAMA8 ~ RAMA11) : Data RAM address (address8 to address10) for RAM reading. Bit 4~5 = 0 : unused Bit6~Bit7 : Un-defined register. These two bits are un-define and their values will variation. Bit 6 (DED) : Interrupt flag of Differential Energy Detector (DED) output data Bit 7 (DEDD) : Output data of Differential Energy Detector (DED) If input signal from EGIN1 and EGIN2 pin to Differential Energy Detector is over the threshold level setting at IOCE PAGE 2 bit 0 (SEDTHD), the DED will extract the zero-crossing pulse waveform corresponding to input signal. RF (Interrupt flags) 7 6 5 4 3 RBF INT2 INT1 INT0 "1" means interrupt request, "0" means non-interrupt Bit 0 (TCIF) : TCC timer overflow interrupt flag Set when TCC timer overflows . Bit 1 (CNT1) : Counter1 timer overflow interrupt flag * This specification is subject to be changed without notice. 2 CNT2 1 CNT1 0 TCIF _________________________________________________________________________________________________________________________________________________________________ 27 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Set when counter1 timer overflows . Bit 2 (CNT2) : Counter2 timer overflow interrupt flag Set when counter2 timer overflows . Bit 3 (INT0) : External INT0 pin interrupt flag If PORT70 ,PORT71,PORT72 or PORT73 has a falling edge trigger signal. CPU will set this bit. Bit 4 (INT1) : External INT1 pin interrupt flag If PORT74 ,PORT75 or PORT76 has a falling edge trigger signal. CPU will set this bit. Bit 5 (INT2) : External INT2 pin interrupt flag If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal. CPU will set this bit. Bit 6 : unused Bit 7 ( RBF) : Interrupt flag for SPI data complete If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit. IOCF is the interrupt mask register. User can read and clear. Trigger edge as the table Signal TCC COUNTER1 COUNTER2 INT0 INT1 INT2 RBF Trigger Time out Time out Time out Falling edge Falling edge Falling/Falling&rising edge Rising edge Controlled by CONT register R10~R3F (General Purpose Register) R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers. VII.4 Special Purpose Registers A (Accumulator) Internal data transfer, or instruction operand holding It's not an addressable register. CONT (Control Register) 7 6 5 4 3 2 INT_EDGE INT TS PAB PSR2 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1 PSR1 0 PSR0 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 28 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4 : undefined Bit 5(TS) : TCC signal source 0 Instruction clock 1 16.384kHz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.16. Bit 6 (INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7(INT_EDGE) : interrupt edge type of P70 0 => P70 's interruption source is a rising edge signal and falling edge signal. 1 P70 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register. Fig.16 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode. The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode. Data Bus Instruction clock 16.384kHz M U X TS M U X PAB SYNC 2 cycles TCC(R1) TCC overflow interrupt WDT WDTE M U X PAB 8-bit Counter PSR0 ~ PSR2 8-to-1 MUX MUX PAB WDT timeout Fig.16 Block diagram of TCC and WDT _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 29 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller IOC5 (PORT5 I/O control, PORT switch, Key tone , LCD bias) PAGE0 (PORT5 I/O control register, PORT switch) 4 3 2 1 0 IOC57 IOC56 IOC55 P9SH P9SL P8SH P8SL 0 Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P80 ~ P83 for low nibble PORT8 1 select SEG64 ~ SEG67 output for LCD SEGMENT output. Bit 1 (P8SH) : Switch high nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P84 ~ P87 for high nibble PORT8 1 select SEG68 ~ SEG71 output for LCD SEGMENT output. Bit 2 (P9SL) : Switch low nibble I/O PORT9 or LCD segment output for share pins SEGxx/P9x pins 0 select normal P90 ~ P93 for low nibble PORT9 1 select SEG72 ~ SEG75 output for LCD SEGMENT output. Bit 3 (P9SH) : Switch high nibble I/O PORT9 or LCD segment output for share pins SEGxx/P9x pins 0 select normal P94 ~ P97 for high nibble PORT9 1 select SEG76 ~ SEG79 output for LCD SEGMENT output.*Bit 4:general register Bit 4 = 0 : unused Bit 5 ~ Bit 7 (IOC55 ~ IOC57) : PORT5 I/O direction control registers. 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (Key tone control, LCD bias control) 7 6 5 4 3 2 1 0 KT1 KT0 KTS 0 BIAS3 BIAS2 BIAS1 BIAS0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3) : LCD operation voltage selection V1 = VDD * (5 - n/15)/5 (BIAS3 to BIAS0) 0000 0001 0010 0011 0100 : 1101 1110 1111 V1 voltage VDD * (5-0/15)/5 VDD * (5-1/15)/5 VDD * (5-2/15)/5 VDD * (5-3/15)/5 VDD * (5-4/15)/5 : VDD * (5-13/15)/5 VDD * (5-14/15)/5 VDD * (5-15/15)/5 Example (VDD=5V) 5V 4.93V 4.86V 4.80V 4.73V : 4.13V 4.07V 4.0V 7 6 5 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 30 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller COMs BIAS MUX VC1 ~ VC5 generator LCD driver for COM and SEG SEGs 4 BIAS3 to BIAS0 VC1 ~ VC5 Fig.17. The relation between bias and V1 to V5 FRAM E COM 0 COM 1 COM 2 V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND SEG dark SEG light V1 V2 V4 V5 GND Fig.18a LCD waveform (1/4 bias) for 1/8 duty, 1/9 duty, 1/16 duty _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 31 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller frame V1 v2 v3 v4 v5 Gnd V1 v2 v3 v4 v5 Gnd V1 v2 v3 v4 v5 Gnd com0 com1 com2 seg V1 v2 v3 v4 v5 Gnd dark V1 v2 v3 v4 v5 Gnd seg light Fig.18b LCD waveform (1/5 bias) for 1/24 duty Bit 4 = 0 : unused Bit 5 (KTS) : Key tone output switch 0 normal PORT67 1 key tone output . Bit 6 ~ Bit 7 (KT0 ~ KT1) : Key tone output frequency and its power control KT1 KT0 Key tone frequency and power 0 0 32.768KHz/32 = 1.024kHz clock and enable 0 1 32.768KHz/16 = 2.048kHz clock and enable 1 0 32.768KHz/8 = 4.096kHz clock and enable 1 1 Power off key tone IOC6 (PORT6 I/O control, PORT switch, LCD driving control) PAGE0 (PORT6 I/O control register) 7 6 5 4 3 2 1 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 Bit 0 ~ Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 32 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller PAGE1 (empty register) PAGE 2 (PORT switch, LCD driving ability control) 7 6 5 4 3 2 1 PCSH PCSL PBS LCDDV1 LCDDV0 0 0 Bit 0 ~ Bit 2 = 0 : unused Bit 3 ~ Bit 4 (LCDDV0 ~ LCDDV1) : LCD driver's driving ability control LCDDV1 0 0 1 1 LCDDV0 0 1 0 1 Driving mode Normal mode (ratio = 1) Weak mode (ratio = 1/2) Strong mode (ratio = 2) Maximum mode (ratio = 4) 0 0 LCDDV0 ~ LCDDV1 are used to select the driving ability of LCD driver. The driving ability is Maximum mode > Strong mode > Normal mode > Weak mode by 1/2 ratio individually. The larger driving ability it is selected, the larger output loading of LCD driver output can be afforded and the more current consumption is occurred. It depends on user's application. Bit 5 (PBS) : Switch I/O PORTB or LCD segment output for share pins SEGxx/PBx 0 select normal PB0 ~ PB7 for PORTB 1 select SEG48 ~ SEG55 output for LCD SEGMENT output. Bit 6 (PCSL) : Switch low nibble I/O PORTC or LCD segment output for share pins SEGxx/PCx 0 select normal PC0 ~ PC3 for low nibble PORTC 1 select SEG56 ~ SEG59 output for LCD SEGMENT output. Bit 7 (PCSH) : Switch high nibble I/O PORTC or LCD segment output for share pins SEGxx/PCx 0 select normal PC4 ~ PC7 for high nibble PORTC 1 select SEG60 ~ SEG63 output for LCD SEGMENT output. IOC7 (PORT7 I/O control, Key strobe(8~15)) PAGE0 (PORT7 I/O control register) 7 6 5 4 3 2 1 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 Bit 0 ~ Bit 7 (IOC70 ~ IOC77) : PORT7(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (Key strobe control register) 7 6 5 4 3 2 0 IOC70 1 0 STRB15 STRB14 STRB13 STRB12 STRB11 STRB10 STRB9 STRB8 Bit 0 ~ Bit 7 (STRB8 ~ STRB15) : Key strobe control bits These key strobe control registers correspond to SEGMENT8 to SEGMENT15. Please refer KEYSTOBE explanation (RE page0). IOC8 (PORT8 I/O control, , Key strobe(16~23)) PAGE0 (PORT8 I/O control register) 7 6 5 4 IOC87 IOC86 IOC85 IOC84 3 IOC83 2 IOC82 1 IOC81 0 IOC80 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 33 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : PORT8(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (Key strobe control register) 7 6 5 4 3 2 1 0 STRB23 STRB22 STRB21 STRB20 STRB19 STRB18 STRB17 STRB16 Bit 0 ~ Bit 7 (STRB16 ~ STRB23) : Key strobe control bits These key strobe control registers correspond to SEGMENT16 to SEGMENT23. Please refer KEYSTOBE explanation (RE page0). IOC9 (PORT9 I/O control) PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 0 IOC90 IOCA (CN1's and CN2's clock and scaling, PORT7 pull high control) PAGE0 (Counter1's and Counter2's clock and scale setting) 7 6 5 4 3 2 CNT2S C2P2 C2P1 C2P0 CNT1S C1P2 Bit 0 ~ Bit 2 (C1P0 ~ C1P2) : Counter1 scaling C1P2 C1P1 C1P0 COUNTER1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3 (CNT1S) : Counter1 clock source 0/1 16.384kHz/MCU clock Bit 4 ~ Bit 6 (C2P0 ~ C2P2) : Counter2 scaling C2P2 C2P1 C2P0 COUNTER2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 7 (CNT2S) : Counter2 clock source 0/1 16.384kHz/MCU clock 1 C1P1 0 C1P0 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 34 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller PAGE1 (PORT7 pull high control register) 7 6 5 4 3 2 1 PH77 PH76 PH75 PH74 PH73 PH72 PH71 Bit 0 ~ Bit 7 (PH70 ~ PH77) : PORT7(0~7) pull high control register 0 disable pull high function. 1 enable pull high function 0 PH70 IOCB (PORTB I/O control, PORT6 pull high control) PAGE0 (PORTB I/O control register) 7 6 5 4 3 2 1 0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 Bit 0 ~ Bit 7 (IOCB0 ~ IOCB7) : PORTB(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (PORT6 pull high control register) 7 6 5 4 3 2 1 0 PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60 Bit 0 ~ Bit 7 (PH60 ~ PH67) : PORT6(0~7) pull high control register 0 disable pull high function. 1 enable pull high function IOCC (PORTC I/O control, TONE1 control) PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOCC7 IOCC6 IOCC5 IOCC4 IOCC3 IOCC2 IOCC1 IOCC0 Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (TONE1 control register) 7 6 5 4 3 2 1 0 T17 T16 T15 T14 T13 T12 T11 T10 Bit 0 ~ Bit 7(T10 ~ T17) : Tone generator1`s frequency divider and power control Please Run in Normal mode . Clock source = 111957Hz T17~T10 = `11111111' => Tone generator1 will has 439Hz SIN wave output. : T17~T10 = `00000010' => Tone generator1 will has 55978Hz SIN wave output. T17~T10 = `00000001' => DC bias voltage output T17~T10 = `00000000' => Power off Built-in tone generator can generate dialing tone signals for telephone of dialing tone type or just a single tone. In DTMF application, there are two kinds of tone. One is the group of row frequency (TONE1), the other is the group of column frequency (TONE2), each group has 4 kinds of frequency, user can get 16 kinds of DTMF frequency totally. Tone generator contains a row frequency sine wave generator for generating the DTMF signal which selected by IOCC and a column frequency sine wave generator for generating the DTMF signal which selected by IOCD. This block can generate single tone by filling one of these two registers. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 35 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller If all the values are low, the power of tone generators will turn off . TONE2 (IOCD PAGE1) High group freq. 1203.8 (0X5D) 1332.8(0X54) 1473.1(0X4C) 1646.4(0X44) TONE1(IOCC 699.7Hz(0x0A0) 1 2 3 A PAGE1) 772.1Hz(0x091) 4 5 6 B Low group freq. 854.6Hz(0x083) 7 8 9 C 940.8Hz(0x077) * 0 # D Also TONE1 and TONE2 are an asynchronous tone generator so the both can be used to generate Caller ID FSK signal. In FSK generator application, TONE1 or TONE2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table. TONE1(IOCC PAGE1) or Freq. (Hz) TONE2(IOCD PAGE1) 0x5D 1203.8 Bell202 FSK Mark bit 0x33 2195.2 Bell202 FSK Space bit 0x56 1301.8 V.23 FSK Mark bit 0x35 2112.4 V.23 FSK Space bit IOCD (Counter1 data, TONE2 control) PAGE0 (Counter1 data buffer) 7 6 5 4 3 2 1 0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's data buffer User can read and write this buffer. Counter1 is a eight bit up-counter with 8-bit prescaler that user can use IOCD to preset and read the counter. ( write = preset) After a interruption, it will reload the preset value. Example: write: IOW 0x0D ; write the data at accumulator to counter1 (preset) Example: read: IOR 0x0D ;read IOCD data and write to accumulator PAGE1 (TONE2 control register) 7 6 5 4 3 2 1 0 T27 T26 T25 T24 T23 T22 T21 T20 Bit 0 ~ Bit 7(T20 ~ T27) : Tone generator 2`s frequency divider and power control Please Run in Normal mode . Clock source = 111957Hz T27~T20 = `11111111' => Tone generator2 will has 439Hz SIN wave output. : T27~T20 = `00000010' => Tone generator2 will has 55978Hz SIN wave output. T27~T20 = `00000001' => DC bias voltage output T27~T20 = `00000000' => Power off IOCE (Counter2 data, Comparator and OP control) PAGE0 (Counter2 data buffer, Comparator control, OP control) 7 6 5 4 3 2 1 0 CN27 CN26 CN25 CN24 CN23 CN22 CN21 CN20 Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2's data buffer User can read and write this buffer. Counter2 is a eight bit up-counter with 8-bit prescaler that user can use IOCD to preset and read the counter. ( write = preset) After a interruption, it will reload the preset value. Example: write: IOW 0x0D ; write the data at accumulator to counter1 (preset) Example: read: IOR 0x0D ;read IOCD data and write to accumulator _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 36 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller PAGE1 (Comparator reference voltage type, PORT switch) 7 6 5 4 3 2 1 0 CMPREF CMPIN3 CMPIN2 CMPIN1 0 0 0 0 Bit 0 ~ Bit 3 = 0 : unused Bit 4 (CMPIN1) : Switch for controlling PORT63 as IO PORT or a comparator input. 0 IO PORT63 1 comparator input Bit5 (CMPIN2) : Switch for controlling PORT64 as IO PORT or a comparator input. 0 IO PORT64 1 comparator input Bit 6 (CMPIN3) : Switch for controlling PORT65 as IO PORT or a comparator input. 0 IO PORT65 1 comparator input Bit 7 (CMPREF) : Switch for comparator reference voltage type 0 internal reference voltage (Come from VDD). 1 external reference voltage PAGE2 (Undefined) 7 6 5 4 3 2 1 0 0 IOCE page2 is un-exist in EM78870, please do not access this register. Bit 0~6 : Undefined. These bits are not allowed to used. Bit 7 : Unused, please clear this bit to 0 or the result of comparator will wrong. 0 IOCF (Interrupt Mask Register) 7 6 5 4 3 RBF INT2 INT1 INT0 Bit 0 ~ Bit 5,7 are interrupt mask enable bits. 0 disable interrupt 1 enable interrupt Bit6 : unused 2 CNT2 1 CNT1 0 TCIF _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 37 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller VII.5 I/O Port The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.19. PCRD Q P R C L D CLK PCWR Q PORT Q P R C L D CLK PDWR IOD Q PDRD 0 1 M U X Fig.19 The circuit of I/O port and I/O control register VII.6 RESET The RESET can be caused by (1) Power on voltage detector reset (POVD) and power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. * The Watchdog timer and prescaler counter are cleared. * The Watchdog timer is disabled. * The CONT register is set to all "1" * The other register (bit7..bit0) _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 38 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller A Address R register Page0 000xxxxx 00xxxxxx xxx00000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000110 xxxxxxxx xxxxxxxx 00000000 10000000 00000000 R register Page1 IOC Register Page0 IOC Register page1 IOC Register Page2 4 5 6 7 8 9 A B C D E F 00000000 xxxxxxxx xxxxxxxx Xxxxxxxx Xxxxxxxx x0000000 Xxxxxxxx Xxxxxxxx Xxxxxxxx Xxxxxxxx 000xxxxx - 11100000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 00000000 00000000 00000000 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 - 00000000 00000000 VII.7 wake-up The controller provided sleep mode for power saving. SLEEP mode , RA(7)=0 + "SLEP" instruction . The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has enable register), user has to turn it off by software. Wake-up from SLEEP mode (1) WDT time out (2) external interrupt (3) /RESET pull low All these cases will reset controller , and run the program at address zero. The status just like the power on reset. Be sure to enable circuit at case (1) or (2). VII.8 Interrupt RF is the interrupt status register which records the interrupt request in flag bits. IOCF is the interrupt mask register. TCC timer, Counter1 and Counter2 are internal interrupt source. P70 ~ P77(INT0 ~ INT1) are external interrupt input which interrupt sources are come from the external. If the interrupts are happened by these interrupt sources, then RF register will generate '1' flag to corresponding register if you enable IOCF register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. CAS pin goes to low. VII.10 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 39 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C Instruction cycle 1 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip 1 0 0000 0001 0100 0014 CONTR 0 0000 0001 rrrr 001r IOR R 0 0000 0010 0000 0020 TBL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 01rr rrrr 00rr MOV R,A 1000 0000 0080 CLRA 11rr rrrr 00rr CLR R 00rr rrrr 01rr SUB A,R 01rr rrrr 01rr SUB R,A 10rr rrrr 01rr DECA R 11rr rrrr 01rr DEC R 00rr rrrr 02rr OR A,R 01rr rrrr 02rr OR R,A 10rr rrrr 02rr AND A,R 11rr rrrr 02rr AND R,A 00rr rrrr 03rr XOR A,R 01rr rrrr 03rr XOR R,A 10rr rrrr 03rr ADD A,R 11rr rrrr 03rr ADD R,A 00rr rrrr 04rr MOV A,R 01rr rrrr 04rr MOV R,R 10rr rrrr 04rr COMA R 11rr rrrr 04rr COM R 00rr rrrr 05rr INCA R 01rr rrrr 05rr INC R 10rr rrrr 05rr DJZA R 11rr rrrr 05rr DJZ R 00rr rrrr 06rr RRCA R _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 40 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller 0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0111 0111 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1110 01rr 10rr 11rr bbrr bbrr bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A C C C None None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC 1 1 1 1 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1 1 1110 100k kkkk 1E8k PAGE k 1 1111 kkkk kkkk 1Fkk ADD A,k VII.11.1 CODE Option Register The controller has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 7 6 5 4 3 2 1 0 /PTB Bit 0(/PTB) : Program ROM data protect bit. 0/1 protect / unprotect When user clear this bit to 0, another person will unable read the originally program code from program ROM. Bit 1 : Unused, must be "1". _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 41 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller Bit 2 ~ Bit 7 : Unused, must be "0"s. VII.11.2 PAD Option /POVD(power on voltage detect) reset can be enabled/disabled by PAD Option. This POVD pad is not shown on the pin assignment. Internally or externally connecting this pad to GND/VDD to enable/disable /POVD reset. /POVD 2.2V reset power on reset Low power Low power detect sleep mode detect without controlled by current reset RA(5) 1 No yes Yes Yes 1uA 0 yes yes Yes yes 15uA VIII.Absolute Operation Maximum Ratings RATING SYMBOL VALUE -0.3 To 6 -0.5 TO Vdd +0.5 0 TO 70 UNIT V V J DC SUPPLY VOLTAGE Vdd INPUT VOLTAGE Vin OPERATING TEMPERATURE RANGE Ta IX DC Electrical Characteristic (Operation current consumption for Analog circuit under VDD=5V VSS=0V) Symbol I_CMP Parameter Operation current for comparator Condition VDD=5V, PT power on Min Typ 0.17 Max Unit mA (Ta=0C ~ 70C, VDD=5V5%, VSS=0V) Symbol IIL1 IIL2 VIH VIL VIHT VILT VIHX VILX VOH1 Parameter Input Leakage Current for input pins Input Leakage Current for bi-directional pins Input High Voltage Input Low Voltage Input High Threshold Voltage Input Low Threshold Voltage Clock Input High Voltage Clock Input Low Voltage Output High Voltage (port5,8,9,B,C) (port6,7) Output Low Voltage Condition VIN = VDD, VSS VIN = VDD, VSS 2.5 0.8 /RESET, TCC, RDET1 /RESET, TCC,RDET1 OSCI OSCI IOH = -6mA IOH = -10.0mA IOL = 6mA 3.5 1.5 2.4 2.4 0.4 2.0 0.8 Min Typ Max 1 1 Unit A A V V V V V V V V V VOL1 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 42 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller (port5,8,9,B,C) (port6,7) Pull-high current Power down current (SLEEP mode) Low clock current (FREEN mode) IPH ISB1 ISB2 ICC Operating supply current (NORMAL mode) IOL = 10.0mA Pull-high active input pin at VSS All input and I/O pin at VDD, output pin floating, WDT disabled CLK=32.768KHz, All analog circuit disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD enable /RESET=High, PLL enable CLK=3.5826MHz, output pin floating,LCD enable, all analog circuit disable -10 1 0.4 -15 4 V A A 50 80 A 1.0 1.3 mA IX AC Electrical Characteristic (Ta=0C ~ 70C, VDD=5V, VSS=0V) Symbol Dclk Tins Tdrh Ttcc Twdt Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period Conditions 32.768kHz 3.5826MHz _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 43 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller XI. Timing Diagrams ins Fig.20 timing _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 44 8/19/2004 (V1.5) EM78P870 8-bit OTP Micro-controller XII. Application Circuit LCD pannel COMMON VC1 11 0.1u 0.1u 0.1u 0.1u 0.1u VDD 27p 27p 0.1u VC2 12 SEGMENT Key matrix VC3 13 VC4 14 VC5 15 VDD,AVDD 18 XIN 16 32.768k XOUT 17 SEG8 PLLC AVSS,GND 19 21 22 24~27 P70 TEST P71 P72 P73 SEG23 EM78P870 SEG10 SEG9 _________________________________________________________________________________________________________________________________________________________________ * This specification is subject to be changed without notice. 45 8/19/2004 (V1.5) |
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